(1) Field of the Invention
The present invention relates in general to semiconductor design technology; more particularly this invention relates to the manufacture of memory Integrated Circuits (IC), and even more particularly to a semiconductor memory IC having an optimized chip area design with enhanced writing speed behavior via technologically adapted data-line selection devices in such memory circuits.
(2) Description of the Related Art
In general, electronic data storage devices built as integrated memory circuits are made up of a large number of memory cells arranged in the form of a matrix or array with rows and columns. These arrays are surrounded by a number of auxiliary elements—also called peripheral circuits—necessary for achieving the purpose of those data storage operations, i.e. writing data into and accordingly reading data from addressed memory cells within that storage device, all this under control of read/write enable and row and column address strobe signals, whereby row and column addresses are extracted from appropriately decomposing the intrinsic memory address. Confining the description to such memory circuits, which constitute the majority of cases in data storage applications, namely to Dynamic Random Access Memories (DRAMs) allows to explain more thoroughly the composition and operation of such circuits. From now on, the items designated with capital letters signify discrete tangible circuit or data elements and circuit blocks in DRAMs. Corresponding to these operations, besides said Memory Cell Array—arrayed in Rows and Columns—with additional Precharge Circuits and Sense Amplifiers (also possibly combined into common blocks) with I/O Gate functionality for the Read/Write operations from and to the Memory Cells—which plainest can be made up of a single transistor and a single capacitor and generically named as Unit Memory Cells in that specific meaning, being part of said Memory Array—the other function blocks present are Data Buffers or special Data I/O (IN/OUT or Input/Output) Driver blocks for Data Input and Data Output, Address Buffers for Memory Addresses—either conjointly or separately used for Rows and Columns, in the latter case then having separate Row Address and Column Address Buffer blocks—Row (also called Word-Line) Decoder (and Driver) blocks and Column Decoder blocks for decoding said Memory Addresses, a Peripheral Control Circuits block for Timing and Control functions also called Control Command block for processing Row and Column Address Strobe signals together with a Read/Write Enable signal for the operating of all these auxiliary blocks. The signals mentioned above as Data Input, Data Output, Memory Addresses, Row and Column Address Strobes, and Read/Write Enable are normally combined in a Data Bus, an Address Bus, and a Control Bus respectively. It shall not remain unmentioned in this context, that Unit Memory Cells for DRAMs can also be made up of three transistor circuits or even more complex configurations and that multi-transistor cells are to be used also in Static RAM arrays, which are not particularly and separately described here however.
Each of the Sense Amplifiers employed in a semiconductor memory device is kind of an amplifying circuit for sensing a microsignal, i.e. a very low voltage or current signal. As typical Sense Amplifiers are known those as Bit-Line Sense Amplifiers and as I/O Sense Amplifiers. The Bit-Line Sense Amplifier is used to sense a microsignal on a Bit-Line pair, which is produced from a Memory Cell, whereas the I/O Sense Amplifier is used to sense a signal transmitted over a Data Bus line pair and amplify it. These tasks may both be combined into operations for one single circuit with additional control elements. As these Sense Amplifiers have various implementations, there are therefore known those of a current or a voltage type, sensing primarily current differences or voltage differences, respectively. A current type Sense Amplifier is used to amplify the amplitude of the current flowing in each Bit-Line depending on a difference between currents which flow in the Bit-Line pair, and this is particularly effective when it is activated at low voltages and its amplitude is small. As the density of semiconductor memory devices increases, simultaneously the operating power supply voltages decrease thereby also reducing current and consequently also alleviating power consumption. In the case of, e.g., DRAMs implemented with CMOS technology, this narrows the range of voltages used to represent one of two binary states. It is therefore desirable to provide the most accurate possible sensing method to determine the state of a Memory Cell. Accurate amplification of voltage levels on Bit-Lines is therefore highly desirable. Due to the trend in decreasing power-supply voltages for semiconductor memory devices, it is difficult to sense the voltage difference between complementary voltage levels on a pair of Bit-Lines, even with specialized voltage type Sense Amplifiers.
In typical DRAMs, data is not directly transmitted from the Memory Cells. Rather, data is temporarily copied to said Sense Amplifiers prior to transmission. Typically, the Sense Amplifiers only store one Row of data. If an operation is to be performed on a Row of data other than the currently stored Row, two operations must be performed. The first operation is referred to as a Precharge operation, where pairs of Bit Lines within the memory are equalized to a midpoint voltage level. The second operation is referred to as a Sense operation, where the Row on which the operation is to be performed is copied onto Sense Amplifiers. Between the Precharge operation and the subsequent Sense operation, the DRAM in question is said to be in a closed state. At all other times, the DRAM is said to be in an open state. In the prior art, DRAMs are configured to determine whether Precharge and Sense operations have to be performed prior to servicing a data transfer request from a controller. Typically, the DRAM performs this determination by comparing the requested Memory Address to the current Memory Address in the DRAM bank. If the two addresses match, then the data is transmitted from the Sense Amplifiers and no Precharge or Sense operations are required. If the addresses do not match, then the DRAM performs a Precharge and Sense operation to load the Sense Amplifiers with data from the appropriate Row. In a memory for transmitting data stored in a Memory Cell to a Bit-Line Sense Amplifier through a Bit-Line pair and storing the data output from the Bit-Line Sense Amplifier a controller circuit is needed, often implemented as Column Selection circuit. The Column Selection circuit includes an Equalizer for equalizing the potentials on the pair of Bit-Lines for compensating signal voltage levels of the Bit-Line pair as a Word-Line is selected. It generates enable signals to operate the Bit-Line Sense Amplifier, which allows data to be transmitted via the Bit-Line pair from the Memory Cell to the Bit-Line Sense Amplifier, and transmitting the data output from the Bit-Line Sense Amplifier to the Data-Line pair.
Memory access to the DRAM contents typically takes place as follows. An address buffer first receives the Row Address and then the Column Address. These addresses are passed to their respective decoders, once decoded, the hereby addressed Memory Cell outputs its stored data, which is amplified by a Sense Amplifier and transferred to a Data Output Buffer by an I/O Gate. The central part of the DRAM is the Memory Cell Array, which is where the data are stored. Such a Memory Cell Array is made up of many Unit Memory Cells, each of which is usually individually addressable and used to store a single bit. Unit Memory Cells are defined by Word-Lines WLx (or Rows) and Bit-Lines BLx (or Columns). The Unit Memory Cell has a capacitor which holds the data in the form of electrical charges, and an access transistor which serves as a switch for selecting the capacitor. The transistor's gate is connected to the Word-Line WLx. The source of the access transistors are alternately connected to the Bit-Lines BLx. Adjacent Bit-Lines thus being represented as a Bit-Line pair, counting together a normal potential (BLx) line and a complementary potential (BLx-bar) line. These pairs of Bit-Lines are then evaluated together, generally by some sort of a differential amplifier called Sense Amplifier. At this level, memory access begins when a Word-Line is selected (via the decoding of a Row Address) thereby switching on all the access transistors connected to that Word-Line. In other words, all the Unit Memory Cells in that particular row are turned on. As a result, charges in the capacitor within each Unit Memory Cell are transferred onto the Bit-Lines causing a potential difference between the Bit-Lines. This potential difference is detected and amplified by a Sense Amplifier. This amplified potential difference is then transferred to the I/O Gate activated based on the Column Address, which in turn transfers the amplified signal to the Data Output Buffer. The Precharge Circuit plays a significant role in detecting memory data during the course of a memory access operation. In advance of a memory access and the activation of a Word-Line, the Precharge Circuit charges all Bit-Line pairs up to a certain potential which usually equals to half of the supply potential Vdd, that is, Vdd/2. The Bit-Line pairs are short-circuited by a transistor—controlled by Equalizer Circuits, mostly part of the Precharge Circuit—so that they are each at an equal potential. The precharging and potential equalization by the Precharging Circuit is important due to the disparate difference in capacitance between the Bit-Lines and the storage capacitor. Since the capacitance of the storage capacitor is far less than that of the Bit-Lines, when the storage capacitor is connected to the Bit-Lines via the access transistor, the potential of the Bit-Line changes only slightly, typically by 100 mV. If the storage capacitor was empty, then the potential of the Bit-Line slightly decreases; if charged, then the potential slightly increases. The activated Sense Amplifier amplifies the potential difference on the two Bit-Lines of the pair. In the first case, it draws the potential of the Bit-Line connected to the storage capacitor down to ground and raises the potential of the other Bit-Line up to Vdd. In the second case, the Bit-Line connected to the storage capacitor is raised to Vdd potential and the other Bit-Line is decreased to ground. Without the Precharging Circuit, the Sense Amplifier would need to amplify the absolute potential of the Bit-Lines. However, because of the relatively small potential change between the Bit-Lines, the amplifying process would be much less stable and unreliable. It should be noted that as the access transistors remain on by the activated Word-Line, the accessed data are written back into the Memory Cells of one Row. Therefore, the accessing of a single Memory Cell simultaneously leads to a refreshing of the whole Word-Line. After the Data Output is completed, the Sense Amplifiers and the Row and Column Decoders are disabled and the I/O Gate block is switched off. At that time, the Bit-Lines are still on the potentials according to the accessed data. The refreshed Memory Cells along the same Row are disconnected from the Bit-Lines by the disabled Word-Line. The Precharge Circuit is activated to lower and increase respectively the potentials of the Bit-Lines to Vdd/2 and equalize them again. The Memory Cell Array is then ready for another memory access. In addition, as previously mentioned, the data are stored in the form of electrical charges in the storage capacitor. Ideally, the charges in the storage capacitor should remain indefinitely. However, as a practical matter, the storage capacitor discharges over the course of time via the access transistor and its dielectric layer thereby losing the stored charges and the represented data. Hence the storage capacitor must be refreshed periodically. As discussed above, during the course of a memory access, a refresh of the Memory Cells within the addressed Row is automatically performed. Due to physical constraints, the size of a single Memory Cell Array is limited. Thus, in order to increase overall memory capacity, Memory Cell Arrays can typically be stacked together to provide for the desired capacity. The Precharge Circuit which performs the precharge and equalization functions as mentioned above may also be incorporated into a Sense Amplifier.
The road map for CMOS Integrated Circuit (IC) technology in semiconductor industry generally is to move to lower power supply voltages. There are many reasons for this trend, but the main reason is a demand for higher integration density and lower power consumption. With the emergence of new, higher performance electronics required for modern, often battery operated devices, such as palm-top computers, personal data assistants, mobile phones, navigation systems etc., it is critical to reduce size and power consumption of their ICs, especially for data storage memory ICs. Because industry is also performance driven, ultra fast CMOS devices have very thin gate oxides that determine the maximum voltage these devices can withstand without causing permanent damage to the device. Each new thrust in technology advancement may therefore yield higher chip and component densities with faster clock speeds and lower power consumption and simultaneously result in smaller chip areas. This substantially improves performance and significantly reduces production cost.
As one means to implement a low power feature for semiconductor memory devices the operating power supply voltage is lowered and a low driving voltage is used, both for high speed operation and reduced power consumption. Various technical supplements have been proposed to improve the operation of the Read/Write Circuits and Sense Amplifiers in such memory devices, mostly adopted for the Read operations of DRAMs. One formation of such supplements is an over-driving scheme of the Sense Amplifier, another one is a multi-level voltage operation scheme for certain circuit blocks in the DRAM, both statically and dynamically applied; whereby besides a normal supply voltage, say Vcc or Vdd, an elevated, by an internal charge pump generated voltage Vpp is introduced for critical auxiliary circuit blocks. In general, if data of a plurality of Memory Cells are transferred onto Bit-Lines, wherein the Memory Cells are connected to a certain Word-Line activated by a Row Address, a Bit-Line Sense Amplifier senses and amplifies the voltage difference between two corresponding Bit-Lines constructing a Bit-Line pair. In the above process, since thousands of Bit-Line Sense Amplifiers start to operate simultaneously, the driving time for the Bit-Line Sense Amplifiers is determined according to the amount of current for driving all the Bit-Line Sense Amplifiers. However, since the operating voltage is lowered according to said trend for low power memory devices, it is difficult to supply sufficient current in a given moment. To overcome that kind of obstacle, over-driving is adopted so as to instantly supply a voltage Vdd higher than an internal core voltage Vcc, onto the power line of the Bit-Line Sense Amplifier at an initiative operating period of the Bit-Line Sense Amplifier (during a period immediately after the charge sharing between a Memory Cell and a Bit-Line).
Technical supplements for an enhancement in Write operations however as subject of this invention are described in the following. Implementations of such Write operation supplements with various auxiliary circuit additions and in different variations of technology at the current state of manufacture in industry are already known. These additions and technologies yet are expensive and it is desirable to find solutions that are less expensive.
The explanations and descriptions above have been dispreaded on purpose so extensively in order to clarify and illustrate the functioning of RAM ICs and emphasize the key role of Sense Amplifiers and their embedding into such devices and in order to foster a better comprehension of their importance for the read/write operations in memory products.
Preferred prior art realizations are implementing DRAMs with pertinent auxiliary circuit additions differently, more complex in function and more expensive in production. It is therefore a challenge for the designer of such circuits to achieve a high-quality, but lower-cost solution. There are various patents referring to such solutions.
U.S. Pat. No. 6,181,193 (to Coughlin, Jr.) teaches using thick-oxide CMOS devices to interface high voltage integrated circuits, whereby in a high voltage tolerant CMOS input/output interface circuit a process feature called “dual-gate” or “thick-oxide” process is used on any devices that will be exposed to high voltage. The thick-oxide devices have a larger capacitance and lower bandwidth, and therefore, preferably, they are only used where exposure to high voltage can cause damage. The remaining devices on the interface circuit may all use a standard process with the thinner oxide, allowing the I/O and the core IC to run at maximum speed. The circuit design topology also limits the number of devices that are exposed to high voltage. Preferably, the protection scheme is broken down into two parts: the driver and receiver.
U.S. Pat. No. 6,661,253 (to Lee et al.) discloses passgate structures for use in low-voltage applications wherein enhanced passgate structures for use in low-voltage systems are presented in which the influence of the threshold voltage Vt on the range of signals passed by single-transistor passgates is reduced. In one arrangement, the gate voltage VGATE−Vt limit for signals propagated through NMOS passgates is raised by applying a higher VGATE; in another arrangement, the Vt is lowered. The use of CMOS passgates in applications where single-transistor passgates have traditionally been used is also presented.
U.S. Pat. No. 6,816,418 (to Hidaka) introduces a MIS semiconductor device having improved gate insulating film reliability. A reliability evaluation value of a gate insulating film of an insulated gate type (MIS) transistor in an unselected state is set to a value equal to or smaller than the reliability evaluation value of the gate insulating film of the MIS transistor in a selected state. An electric field applied to the gate insulating film is determined in accordance with the reliability evaluation value. Therefore, it is possible to the gate insulating film applied electric field of the MIS transistor in the unselected state lower than the electric field in the selected state to assure the reliability of the gate insulating film of the MIS transistor in the unselected state. Thus, the reliability of the gate insulating film of the MIS transistor in the unselected state is assured, and a semiconductor device with an improved gate dielectric characteristic is obtained.
In the prior art, there are different technical approaches for achieving the goal of sped-up Write operations for integrated memory circuit in DRAM configuration. However these approaches use often solutions, which are somewhat technically complex and therefore also expensive in production. It would be advantageous to reduce the expenses in both areas.
Although the above mentioned patents describe circuits and/or methods close to the field of the invention they differ in essential features from the circuit, the system and especially the method introduced here.